Senior Embedded Engineer

 

Gururaj

G100602

 

PROFESSIONAL SKILLS:

 

• 9+ years of experience in CPU Validation, Systems Programming, Embedded Systems and Network Processors.

IA32 Processors:

·         Enterprise Server Xeon Processor Pre-Si and Post Si validation and life cycle.

·         RTL debug for server Processors, Post Si debug capabilities, DFx features.

·         CPU Quick Path Interconnect and FBD Bus Protocol analysis.

 

Network Processors and Network Protocol Development:

·         Intel IXP Network Processor Architecture, MPLS, L2/L3 Routing, Diffserv, PPP, ATM Network Protocol Implementation in Data plane using microcode.

·        VxWorks Ethernet Network Driver Development.

 

Programming and Embedded Systems:

·        Remote access server features development in a pSOS RTOS environment, Flash Driver Development for an Embedded Microcontroller product.

·        Assembly, C, VC++ Programming, IXP Network Processor Microcode Development.

 

EDUCATION:

 

• Bachelor of Engineering in Electronics & Communication.

Patent Filings, Publications and Demos

 

·         Packet header alignment optimization for Network Processors (US Patent filed).

·         Critical section microblock optimization by controlling thread execution (US Patent filed).

·         Published papers – Pseudo Ethernet Driver Optimization, Scratch ring framework for NP.

·         Papers on Cache Coherency Protocol Checking in Quick Path interconnect based systems.

·         Paper on FSDB and emulators for pre-si validation.

·         Demos - CPU Quick Path Interconnect & fully buffered DIMM Bus Protocol analyzer Demo in Intel Design Technology Conference, Demo on Intel IXP network processor in Intel Developer Forum, IT.COM and ICT events.

 

PROFESSIONAL EXPERIENCE:

9+ years of experience in CPU Validation, Systems Programming, Embedded Systems and Network Processors.

 

Intel Experience

·        Worked as a Senior Component Design Engineer for Pre-Si Processor Architecture Validation for next generation Intel Xeon Processor.

(From Oct 2007 - Till Date thru Axiom Sources LLC, MD).

·        Worked as a Senior Component Design Engineer for Pre-Si processor Architecture Validation for next generation Intel Xeon Processor.

(From Oct 2006 to till date).

·         Responsible for validation of particular set of fubs, development of test plan, checkers/protos and debug of full chip in RTL environment.

·         Worked as a Lead - Debug Tools and Emulation group for Intel Corporation in Platform System Validation group.

(From August 2003 to Sep 2006).

·         Worked as Software Engineer for Intel Network Processor Division from August 2000 to August 2003 date.

VXL Instruments Experience

 

• Worked as Software Engineer for VXL Instruments Limited, from Jan 1999 to July 2000.

CAREER PROFILE:

 

Axiom Sources LLC, MD

 

Client: Intel Technology, OR

From Oct 2007 – Till Date thru Axiom Sources

Senior Component Design Engineer

Aug 2000 to Till date

1.  Project Title: Pre-Si Validation of Quick Path Interconnect based Multicore Xeon MP Processor

Project        :  Multi Core Xeon processor

Period         :  Sep 2007 to till date

 

Responsibilities:

 

·                     Currently working on pre-si Full Chip validation of next generation Quick
            Path Interconnect based multi core Xeon processor.

·                     Responsible for Intel architectural features like paging, memory operations,
            Virtualization technology, interrupts, Segmentation, Protected mode.

·                     Writing test plans to cover various features, debugged failures, 0in assertions
            and achieved desired pass rates.

·                     Developing different system topologies & configurations with the support
            of bus functional models.

 

OS                       : UNIX

Environment     : System verilog, Specman, IA32 Assembly, Perl, C.

Tools                  : nWave Debussy

 

2.  Project Title    : Pre-Si Validation of Multi-Core Xeon MP Processor

     Project             : Multi Core Xeon processor

     Period              : Oct 2006 to till date

 

Responsibilities:

·         Worked on pre-si Full Chip validation of next generation multi core Xeon processor.

·         Responsible for validation of particular set of fubs, testplan development, and debugging test failures found during RTL regressions using RTL environment and root cause the failure with design team.

·         Writing test plan and test execution to achieve coverage for the given fubs of FC.

·         Work involves development of assembly tests as per plan, proto checkers, specman tests for cluster level validation and signal coverage.

·         Worked on EMON test plan, init pin validation, fuse and Power on configuration validation.

OS                        : UNIX

Environment      : RTL in HDL, Specman, IA32 Assembly, C.

 

3.  Project Title        : Debug tool and Emulation for Quad Core Products

Project               : Quad Core Products for UP, DP and MP configuration

Tool Name                   : Interrupt based debug tools and Emulation

Period                : Nov 2005 to Aug 2006

Team size           : 5

 

Responsibilities:

 

·         Led a team of 5 people for successful delivery of Interrupt based debug tools, Emulation and ITP/TAP based Debug tools to the Post Si Validation team.

·         I am also responsible for working with system validation customers and stakeholders to support debug tools for various products.

·         Contributed towards successful readiness of QC CPU products.

 

OS                        : UNIX

Environment       : QC RTL, Emulation, C, IA32 Assembly.

 

4.  Project Title        : Multi Link CPU Interconnect & FBD Bus Protocol Analyzer for next generation server products.

Period                : Apr 2004 to Aug 2006

Team size           : 5

 

Description:

 

·         A bus protocol analyzer for CPU Interconnect and FBD (Fully Buffered DIMM) that takes up bus traces from Socket to Socket links and FBD links from integrated memory controllers post processes the trace to provide different levels of debug information.

·         It provides a packet level view, multi link event correlation across several links, transaction level view and an interface to check Bus Protocol Rules.

·         The tool also abstracts trace capture Device Trigger Programming complexities from user.

 

Hardware Details:      

·        Probes for high speed trace capture, Goldbridge, Logic Analyzers, Trace capture device validation platform and NUMA based multi processor platform.

 

Software Details:       

·         Microsoft Visual Studio v6.0 on Windows XP.

Responsibilities:

 

·         Led a Team of size 5 to develop and validate layers of interconnect protocol stack.

·        Developed Quick path interconnect transaction disassembly for Multi Socket system and FBD links.

·         Multi Socket Interconnect Protocol rule checking capability integrated with the tool.

·         Time correlate traces and event correlation across links.

·         Integration of tool with a Trace capture device validation platform.

·         Trigger panels to configure probe triggers and trace data retrieval.

·         Tool validation done with Multi Socket Interconnect Bus Functional Model, Socket Full Chip traces.

·         Trigger and filter verification on Trace capture device validation platform.

·         Worked on DFx requirements for interconnect based Xeon processor.

·         Responsible Cache coherence protocol debug for interconnect based, multi core architecture.

·         Worked on RTL debug for Xeon Full Chip model.

·         Defined debug strategy, Debugged and root caused several issues in interconnect logic. 

·         Delivered debug strategy for link layer credit exchange and flow control.

      OS                         : Windows XP and UNIX

Environment       : Visual Studio 6.0, Bus Functional Model

 

5.  Project Title        : Interrupt Based Debug tool

Period               : Nov 2003 to May 2004.

Role                  : Team Lead

Team size          : 3

Project Details:

 

This is a debug tool that helps in quick debug of Post Si failures.

 

Responsibilities:

·         Resolved tool related issues when used on different IA32 based Xeon platforms.

·         Worked on Front Side Bus protocol and transaction decoding of traces captured from LA.

·         Involved in pre-si readiness of tool through verification on Emulator and RTL model.

·         Tool Execution on Xeon based systems, Tool chain user guide document for tool users.

 

OS                         : Linux

Environment       : C, IA32 Assembly on Xeon Platform, CoBALT Emulator

 

6.   Project Title       : MPLS and Diffserv Multi service switch application

 Period               : Mar 2002 to Aug 2003.

 Role                  : Software Engineer

 Team size          : 5

Project Details:

 

·         A Multi service switch for MPLS and diffserv applications over multiple layer 2 protocols like PoS, TCP, Ethernet and ATM.

·         The project implemented edge and core router functionality for MPLS, IPv4 and diffserv protocols on Intel IXP2400 Network processor.

Hardware Details:

·         Dual IXP2400 development system with multiple media cards.

·         Media cards are 4xOC12 PoS/ATM interfaces and 4x1Gbps Ethernet cards, IXIA Network Traffic analyzer for Ethernet traffic and Interwatch 96000 Network analyzer for PoS/ATM traffic.        

                       

Software Details:         

·        IXP2400 Developer workbench on simulator environment.

·         VxWorks running on Xscale. MPLS, IPv4, WRED, QM, Scheduler microblocks.

·         RFC3031, RFC3032, RFC3270 compliance for MPLS blocks.

 

Responsibilities:

 

·         Multi service switch application basically has MPLS diffserv and non-diffsrev core & edge router pipelines, IPv4 diffserv and non-diffserv egde and core pipelines.

·         Worked on MPLS data plane modules, which basically consists on ILM forwarder and FTN forwarder microblocks.

·         ILM forwarder provides core and egress edge router functionality and FTN forwarder block supports ingress edge router functionality.

·         Incorporated RFC3270 MPLS diffserv features which support pipe and uniform models.

·         Worked on Weighted Random early Drop (WRED) diffserv block for congestion avoidance.

·         Worked on packet Tx block on egress side to meet 2xOC12 rates.

·         Also worked on single microengine Rx-Tx block that supports 2xOC12 rates and provides 25% headroom in forwarder blocks.

·         Worked on migrating transactor projects to IXP2400 hardware platform. Porting of MPLSoEthernet pipelines on hardware with and without core components. Worked on Tornado applications for integrating core components and configuring route tables. Worked on MPLSoPPP and MPLSoATM projects on transactor.

·         Worked on System requirements spec, design, unit test, system test documents.

My Role:

·         Design & development of MPLS blocks, WRED block and packet TX block on data plane using Intel IXP2400 network processor microcode and microC programming languages.

·         Carried out unit testing and system testing of MPLS pipelines on transactor and hardware.

·         Development of VxWorks applications for integrating core components for ingress and egress pipelines on control plane.

·         Code optimization in IPv4 microC blocks and performance enhancement in 2x1Gbps IPv4 application

 

OS                         : VxWorks on XScale

Environment       : C, Intel IXP2400 microcode and microC network  processor programming

 

7.  Project Title        : TMS Network Driver (Tornado for Managed Switches)

Period                : Dec 2000 to Feb 2002

Role                   : Software Engineer

Team size           : 2

Project Details:

 

TMS Driver is a VxWorks END (Enhanced Network Driver) that provides the connectivity between Layer 3 forward microcode (Data Plane) and the Wind River Systems TMS (Control Plane), to exchange packets and control information.

 

Hardware Details:

·         Intel IXP1200 Evaluation system with 8 10/100 and 2 gig ports.

·         Intel IXP1200 Spectacle Island with 16 10/100 and 2 gig ports.

·         IXIA packet generator, used for testing.

 

Software Details:

·         VxWorks, Tornado development environment L3 forward microcode. (RFC1812 compliant)                         

 

Responsibilities:

 

·         TMS Driver basically has 3 modules. Init module, packets transmit/receive module and hwApi module.

·         Init module initializes driver modules, loads microcode onto micro engines and starts all instances of driver.

·         Transmit and receive module contains send, receive and poller routines that send/receive packets to/from L3 microcode.

·         Poller dequeues packets from the core port (Queue where micro engines enqueue packets) and gives it to receive routine of particular instance of driver.

·         Receive routine forms an mBlk and gives it to VxWorks network stack.

·         Send routine enqueues packets to transmit queues of L3 microcode. These functions have support for both 10/100 as well as gig ports.

·         HwApi module provides APIs to configure switch and update routing tables used by L3 micro code. These functions are implemented using ioctl call.

·        Optimizing IPv4 microC forwarder application and achieved 15% enhancement in Performance for 2x1Gbps IPv4 application, 16x100Mbps IPv4 application.

My Role:

·         Design & development of all modules of TMS Ethernet Network driver for both, IXP1200 eval boards.

·         Carried out unit & system testing of TMS driver with L3 application.

 

OS                         : VxWorks. (RTOS)

Environment       : C and Intel IXP1200 microcode

VXL Instruments Ltd. 

Jan 1999 to July 2000

Software Engineer

1. Project Title  : Remote Access Server (RAS).

 

Project Details:

 

RAS is a product that allows a user to gain access to a network (LAN or WAN) and to execute various network commands, using (UNIX like) command line Interface. Usages of all commands are UNIX type.

 

Hardware Details:   

·         MPC860 Power PC (Motorola Processor), 8 Mb flash & 64Mb SRAM.       

·         16 ports with 2481 CLCD interface. (Cirrus Logic). 1 console port to configure RAS parameters, 1 Parallel Printer port, 1 FEC Ethernet interface & AUI ethernet interface.

Software Details:         

·         pSOS. (Real time OS development), TCP/IP stack.

      Responsibilities:

 

·         A user on UNIX terminal can connect to RAS using one of the 16 ports & can execute many commands like ping, telnet, rlogin, ftp, revtelnet, SLIP, PPP etc.

·        Only super user can execute configuration commands like ifconfig, ifset, portset etc, which modify the RAS parameters.

·        RAS parameters can be modified temporarily or permanently.

·         Facility to open multiple telnet sessoins & to switch between different sessions on a RAS port.

·         Remote configuration of RAS can be done by opening a telnet session to RAS telnet daemon.

My Role:

·         Design & development of CLI (command line interface) for RAS ports, parallel printer connectivity, console port, pSOS real time OS & implementation of various network commands like ifconfig, route, arp etc.

 

2. Project Title    : Point of Sale (PoS).

 

Project Details:

 

·         PoS is an embedded product which aims to provide easy billing facility for all kinds of shops. 

·         Used flash to store the firmware and the database which fits a on a standalone terminal box.

 

Hardware Details:  

·         512K flash. (SST), 128K NVSRAM. (Dollas chip with Real Time Clock).

·         Amd188es microcontroller.

 

Software Details:  

·         TCP/ IP Stack, C, x86 assembly.

My Role:

 

·         I was involved in design & development of User interface, flash Database (for Point of Sale & Kitchen order ticket), flash driver, (parallel & serial) printer driver, weighing scale driver, database Recovery, software maintenance & writing testing tools.

 

3. Project Title     : Winlinx Thin Client Solutions.

 

·         This project aims to add UNIX like multi-user capabilities for windows based Terminals.

·         Design & development of user interface for loading various network interface drivers.

Academic Project:

 

  Project Title: Teleconferencing with audio input on a Novell Netware LAN.